1. Field of the Invention
The present invention relates to a connection verification apparatus for verifying connections between a plurality of logic blocks constituting a semiconductor integrated circuit or the like during function design or logic design.
2. Description of Related Art
FIG. 15 is a block diagram showing a configuration of a conventional connection verification apparatus. In FIG. 15, the reference numeral 1 designates a logic block (called BLK-Y from now on) constituting a semiconductor integrated circuit, for example; 2 designates an input terminal of the BLK-Y 1; 3 designates an output terminal of the BLK-Y 1; 4 designates a logic block (called BLK-A from now on) constituting the semiconductor integrated circuit; 5 designates an input terminal of the BLK-A 4; 6 designates an output terminal of the BLK-A 4; 7 designates signal lines connecting between the output terminal 3 of the BLK-Y 1 and the input terminal 5 of the BLK-A 4; 8 designates a verification data generating section for supplying the input terminal 2 of the BLK-Y 1 with the verification data for verifying the functions (or logic) of the BLK-Y 1 and BLK-A 4 (including the interconnection between the BLK-Y 1 and BLK-A 4); 9 designates a logic data input section for receiving the logic data output from the output terminal 6 of the BLK-A 4; 10 designates an expected value generating section for generating an expected value of the logic data output from the output terminal 6 of the BLK-A 4; and 11 designates a connection verification section for verifying the interconnection between the BLK-Y 1 and BLK-A 4 besides the function (logic) of the BLK-Y 1 and BLK-A 4 referring to the verification data generated by the verification data generating section 8, the logic data supplied from the logic data input section 9 and the expected value generated by the expected value generating section 10.
Next, the operation of the conventional connection verification apparatus will be described.
To verify the interconnection between the BLK-Y 1 and BLK-A 4, the verification data generating section 8 supplies the input terminal 2 of the BLK-Y 1 with the dedicated verification data. In other words, it supplies the input terminals I1–Ik with the verification data, each bit of which consists of the signal value “1” or “0”.
Receiving the verification data from the input terminal 2, the BLK-Y 1 carries out prescribed logic processing in accordance with the verification data, and outputs the resultant logic data via the output terminal 3.
In this way, when the interconnection between the output terminals Y1–Yn of the BLK-Y 1 and the input terminals A1–An of the BLK-A 4 is normal, the logic data the BLK-Y 1 outputs is supplied to the input terminal 5 of the BLK-A 4 via the signal lines 7.
Receiving the logic data via the input terminal 5, the BLK-A 4 carries out the prescribed logic processing in accordance with the logic data, and supplies the resultant logic data to the output terminal 6.
The logic data input section 9 receives the logic data output from the output terminal 6 of the BLK-A 4. In other words, it receives the logic data, each bit of which consists of the signal value “1” or “0”, via the output terminals O1–Om.
Referring to the verification data generated by the verification data generating section 8, the logic data supplied from the logic data input section 9 and the expected value generated by the expected value generating section 10, the connection verification section 11 verifies the interconnection between the BLK-Y 1 and BLK-A 4 along with the functions of the two blocks.
More specifically, the connection verification section 11 verifies the interconnection between the BLK-Y 1 and BLK-A 4 by verifying the logic processing of the BLK-Y 1 when the verification data is supplied, by verifying the logic processing of the BLK-A 4 when the logic result of the BLK-Y 1 is supplied, and by comparing the logic data (logic result of the BLK-A 4) output from the output terminal 6 of the BLK-A 4 with the expected value generated by the expected value generating section 10.
With the foregoing configuration, the conventional connection verification apparatus cannot verify the interconnection between the BLK-Y 1 and BLK-A 4 until it completes the verification of the logic processing of the BLK-Y 1 and BLK-A 4. Accordingly, it has a problem in that as the logic processing of the BLK-Y land BLK-A 4 increase in complexity, the verification of the interconnection between the BLK-Y 1 and BLK-A 4 becomes more difficult.